Pioneer cx 893 service manual

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Figure 1 below shows the block diagram. This block controls the output from the block LD to be consistent with the monitor diode. The block consists of IC 102 and turned to LD ON when LDON (6 pin) is H and to LD OFF when LDON is L. LD output level is set with the voltage value of LDVAR and is usually around 2.4 V. 2 CX-893 1. CIRCUIT DESCRIPTION 1.1 APC Part Fig.1 1.2 RF amplifying part The block amplifies the pickup output signal and generates RF and ADIP signals. This block mainly consists of IC101. REFO part REFO (+1.5 V) is the reference voltage for the servo. The signal is resistive divided at the IC (REFI: 5 pin) and output to 6 pin through buffer. This signal will be the reference for RFIC. RF signal amplifying part Figure 2 below shows the block diagram. The signal which is I-V converted at the pickup is input to the RF1-4 (1-4 pin). Gain at the I-V amplifier contained in the PU is switched depending on the disc types. The switching is controlled by OPICGA (IC401, 61 pin) and H is output at Premaster DISC and L is output at Recordable DISC. The signal input from the I-V amplifier is operated with the contained resistance and amplifiers (A1, A2) and the signal (RF1 + RF2 + RF3 + RF4) (POUT) and the signal (RF1 + RF2 + RF3 - RF4) (GOUT) are generated. Each of POUT and GOUT is equipped with an analog switch. The switches are controlled with the DISC signal (bits on microprocessor serial communications). The POUT signal is output through 48 pin when the DISC signal is H (PIT mode) and GOUT signal is output through 47 pin when the DISC signal is L (GRV mode).These signals are input to EFMAGC (45 pin) through the coupling capacitors (C133, C112) and transmitted to the AGC circuit and filter part to be output from EFMO (40 pin). The EFMO is maintained at almost same level (approx. 1.5 Vpp) with the AGC circuit. These signals are input to the signal processing part (IC201: 3 pin) and used for data processing and spindle control when playing a Premaster Disc.

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3 CX-893 Fig.2 ADIP signal amplifying part Figure 3 shows the block diagram of this part. The block generates the ADIP signal which exists only on a Recordable DISC of a MD. Signals input to RF1 and RF2 (1,2 pin) are transmitted through the AGC part and the filter part to be output to 22KO (32 pin). The 22KO is designed to be maintained at almost same level (approx. 1.2 Vpp) with the AGC circuit. However, fluctuation of about +0.5V may be observed due to core components, responsibility of tracking servo, etc. The signal is then converted to 1 and 0 signal with the comparator C1, input to the signal processing part (IC201:11 pin), and used for address control when playing disc for recording and spindle control. *Will not be used when Premaster Disc is played. C1 Fig.3