Onkyo TXSR 8250 Service Manual

Page 1

TX-SRSOZ/E/8250/HT-R520

Ref. No. 3797

ONKYO SERVICE MANUAL 2"

AV RECEIVER

MODEL TX-SR502
TX-SR502E
TX-SR825O
HT-R520

56130"
mm 908
m... E3;
l: 3%?
{sf-((33 513..
@
Others
L.=.J RC-SGQM
TX-SR502 Black, Golden and Silver models TX-SR502E Black and Silver models
MDD, MDC 120V AC, 60Hz l MPP | 230-240V AC, SOHZ l
35% M f§§§3§§ovz§§vi%H§O/60H TX'S825°G°'""°'
- , z
MGK, MGR, MGQ 220-230V AC, 50/60Hz MGR I 220230" AC 50mm

HT-R520 Black and Silver models

l MDD,MDC | 120VAC, 60Hz l

SAFETY-RELATED COMPONENT
WARNING! !

COMPONENTS IDENTIFIED BY MARK A ON THE
SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE

CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK.

REPLACE THESE COMPONENTS WITH ONKYO
PARTS WHOSE PART NUMBERS APPEAR AS SHOWN
IN THIS MANUAL.

MAKE LEAKAGE-CURRENT OR RESISTANCE
MEASUREMENTS TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE
SUPPLY CIRCUIT BEFORE RETURNING THE
APPLIANCE TO THE CUSTOMER.

ONKYO.

IMAGINATIVE SIGHT & SOUND

Page 45

IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-1

Q181: BU1924FS (RDS decoder)-1
BLOCK DIAGRAM

MUX

Vref

me (5) 7'I'7

[H

81h Switched
capacitor filter

antival iasing
Ii Iter

l

Analog
Power su pply

comparator

2/E/8250/HT-R520

(1e) FICLK

i

(1) QUAL

VSSI (6)
E]
PLL - FIDATA
57km PLL Blvphase Diflerential (2)
VDDQ (12) RDS/ARI 1187.5Hz decoder >decoder I9
>
Digital
Power supply
V552 [101) I
Reference Measurement
clock circuit
(13) D (14) (DH (9)
XI XO T1 T2

TERMINAL DESCRIPTION

Pin No. Pin name Description
1 QUAL Output terminal of demodulator quality signal.
2 FIDATA Output terminal of demodulator data.
3 Vrel Input terminal of reference voltage.
4 MUX Input terminal of composite signal.
5 VDDI Analog power supply.
6 V551 Analog power supply.
7 Vssa Ground.
8 CMP Input terminal of comparator.
9 T2 Input terminal for test mode.
10 T1 Input terminal for test mode.
11 Vssa Digital power supply.
12 VDD2 Digital power supply.
13 XI Connect to oscillator.
14 X0 Connect to oscillator.
15 (N.C.)
16 FICLK Output terminal of demodulator clock.

Page 52

2/ 250/HT-R52

IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-8
0701: CS494003CQZ (Multi-Standard Audio Decoder)-2
TERMINAL DESCRIPTION

FILT1 - Phase-Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.

FILT2 - Phase Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.

CLKIN, XTALI - External Clock Input/Crystal Oscillator Input
CS494003 clock input. This pin accepts an external clock input signal that is used to drive the internal core logic. When in internal clock
mode (CLKSEL == VSS), this input is connected to the internal PLL from which all internal clocks are derived. When in external clock
mode (CLKSEL == VDD), this input is connected to the DSP clock. Alternatively, a 12.288 th crystal oscillator can be connected between
XTALI and XTALOI INPUT

XTALO - Crystal Oscillator Output
Crystal oscillator output. OUTPUT

CLKSEL - DSP Clock Select
This pin selects the internal source clock. When CLKSEL is low, CLKJN is connected to the internal PLL from which all internal clocks are derived.
When CLKSEL is high, the PLL is bypassed and the external clock directly drives all input logic. INPUT

FDATO~FDAT7 - DSPAB Bidirectional Data Bus
In parallel host mode, these pins provide a bidirectional data bus to DSPAB. These pins have an internal pull-up.
BIDIFIECTIONAL - Default: INPUT

FAO, FSCCLK - Host Parallel Address Bit Zero or Serial Control Port Clock
In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In serial host mode, this pin serves
as the serial control clock signal, specifically as the SP1 clock input. INPUT

FA1, FSCDIN - Host Address Bit One or SPI Serial Control Data Input
In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In SPI serial host mode, this pin serves
as the data input. INPUT

FHSt, W, FR/W - Mode Select Bit 1 or Host Parallel Output Enable or Host Parallel Rm
DSPAB control port mode select bit 1. This bit is one of 3 control port select hits that are sampled on the rising edge of RESET to determine the control
port mode of DSPAB. In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel host mode, this pin serves
as the read-high/write-low control input signal. In serial host mode, this pin can serve as the external memory active-low data-enable output signal.
BlDIFtECT/ONAL - Default: INPUT

FHSO, W, fl - Mode Select Bit 0 or Host Write Strobe or Host Data Strobe
DSPAB control port mode select bit 0. This bit is one of 3 control port select bits that are sampled on the rising edge of RESET to determine the control
port mode of DSPAB. In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin
serves as the active-low data-strobe-input signal. In serial host mode, this pin can serve as the external-memory active-low write-enable output signal.
BlDIFtECTIONAL - Default: INPUT

FCS - Host Parallel Chip Select, Host Serial SPI Chip Select
In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low chip-select input
signal. INPUT

FHSZ, FSCDIO, FSCDOUT - Mode Select Bit 2 or Serial Control Port Data Input and Output, Parallel Port Type Select
DSPAB control port mode select bit 2. This bit is one of 3 control port select bits that are sampled on the rising edge of RESET to determine the control
port mode of DSPAB. In SPI mode this pin serves as the data output pin. In parallel host mode, this pin is sampled at the rising edge of RESET to
configure the parallel host mode as an Intel type bus or as a Motorola type bus. BIDIFIECTIONAL - Default: INPUT

FINTFIEQ - Control Port Interrupt Request
Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has outgoing control data that should be read by the host.
OPEN DRAIN I/O - Requires 3. 3K Ohm Pull-Up

FSCLKN1, STCCLK2 - PCM Audio Input Bit Clock
Digital-audio bit clock input. FSCLKNI operates asynchronously from all other DSPAB clocks. In master mode, FSCLKNI is derived from DSPABs
internal clock generator. The active edge of FSCLKNI can be programmed by the DSP.
BIDIRECTIONAL - Default: INPUT