Onkyo TXSR 705 Service Manual

Page 1

ON KYO SERVICE MANUAL

AV RECEIVER

MODEL TX-S R705
MODEL TX-SA705

TX-SR705/SA705

Ref. No. 3997
072007

10>©C®©

TX-SR705 Black, Golden and Silver models

RC-693M

B MDC, S MDC, G MDT

120V AC, 601-12

B MMP, MMA, S MMP, MMA

220-240V AC, SOHZ

B MMO, S MMO

220-240V AC, 50/60Hz

G MMQ, MMK, MMT

220-240V AC, 50/60Hz

TX-SA705 Golden models

IGMMR

220-240V AC, 50/60Hz

SAFETY-RELATED COMPONENT
WARNING! !

COMPONENTS IDENTIFIED BY MARK A ON THE
SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE

CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK.

REPLACE THESE COMPONENTS WITH ONKYO
PARTS WHOSE PART NUMBERS APPEAR AS SHOWN
IN THIS MANUAL.

MAKE LEAKAGE-CURRENT OR RESISTANCE
MEASUREMENTS TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE
SUPPLY CIRCUIT BEFORE RETURNING THE
APPLIANCE TO THE CUSTOMER.

ONKYO®

IMAGINATIVE SIGHT SI SOUND

Page 100

SR70 SA7

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -40
08001: FLI8125-LF-BC (Video Processor)

BLOCK DIAGRAM
24-bit Pattern
Input Port Generator
3:13 Image Processing Controller
CVBS VBI Slicer I _
Inputs _ g C T g a ,_< 24-bitRGB/
. m - - ._ .
S-Vldeo Analog Front 8 g a g g g 3% g E < 5 fl 5 Output I 18-brtRGB/
Inputs End r g g (3 + (-3 '5, 1: 9 g c 5 E 3 $ 9 + Formatteri 16-bItYUV
D 4> a 85 gfigog 0 o 'TTLOutput
YFrFb/RGB S 5 Lu < : DUAL LVDS
Inputs YC_
Sync Stripper Processing
Input
Format .
easummem Embedded ROM RAM DDCZbI
Micro-processor Interface Interface Interface
Ban dwlfgt: Low Internal Micro- I II I 24"!
I .
Analog Bamdth processor Bus I I Controller
Inputs -- 1
IR 1 GPIOs
IR Sensor Interface External ROM I
Input

FEATURES
INTEGRATED TRIPLE ADC FAROUDJA DCDI - EDGET"
I RGB/YPbPr suppori up to 135MHz I Edge Correction
I SCART - RGB + Fast Blank supporl - EIiminaIes objectionable stair casing
I Interlaced and progressive scan - Enhances clarity and realism
I External OSD support I Horizontal Enhancement
DIGITAL INPUT PORT I Adapiive Contrast and Color

I 24-bit re-configurable input porI I Active COIN Management

DIGITAL OUTPUT

' 18/24-bit 85MhZ TTL ouiput

I Dual LVDS up to SXGA

I Energy Specirum Managemem for reducing

INTEGRATED 2D VIDEO DECODER
I Worldwide NTSC/PALISECAM suppori
I Macrovision / VCR trick mode support

EMBEDDED MICROPROCESSOR EMI
I Turbo 186 core I Programmable CLUT for gamma correcIion
I Internal RAM/ROM 05D CONTROLLER

I Serial Flash / Parallel ROM support

I 2-wire slave controller, UART I JTAG suppori I Programmable Font scalar to meeI TeIeIext
I Internal RESET Controller requirements.

I Up to 4 windows: 1, 2 or 4-bits per pixel color

I GPIOs , Low Bandwidth ADC- 6 input VBI SLICER

- I r - dI i rf
" 'a re " e ace - V-Chip, Closed Captioning, XDS, CGMS,

W W88 decode

I Independent H & V scaling facIors I Teletext 1'5 supporl
' 42222 YPbPr or 42414 RGB scaling JTAG SUPPORT

I Anamorphic scaling (non-linear) . Boundary Scan supporl

Page 106

SR70 SA7

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -46
08001: FL|8125-LF-BC (Video Processor)

TERMINAL DESCRIPTION(5/8)

System Interface

Pin Name No IIO Description

GPIO13/PWM2 51 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
external use. Else, this pin is available as General Purpose Input/output Port.

GPIO14/PWM3/ 52 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for

SCART16 external use. Or it can be programmed to sense the Fast Blank Input signal from a
SCART l/P source. Else, this pin is available as General Purpose Input/output Port.

TDO 55 O This Pin provides the Output Data in case of Boundary Scan Mode.

HSYNC1 156 l Horizontal Sync signal Input-1. Used when Analog RGB component signal carries

separate HSYNC signal. Has programmable Schmitt trigger.

VSYNC1 157 l Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate
VSYNC signal. Has programmable Schmitt trigger.

XOSDACLK 101 O Clock Output meant for External OSD Controller

XOSD_HS 102 0 Horizontal Sync Output meant for External OSD Controller

XOSDAVS 103 0 Vertical Sync Output meant for External OSD Controller

XOSDFLD 104 0 Field Signal Output meant for External OSD Controller

PDZO/B4/GPIOO 86 IO These Pins provide the Panel Data as shown in the TTL Display Interface Table below.
PD21/BS/GPIO1 37 These are available as General Purpose Input / Output Pins when not used as Panel
PD22/BG/GPIOZ 88 Data.

PD23/B7/GP|03 89

LVDS Display Interface

Pin Name No IIO Description

PBIAS 53 0 Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
PPWR 54 0 Panel Power Control Uri-state output, 5V- tolerant]
AVDD_LV733 56 DP Digital Power for LVDS Block. Connect to digital 3.3V supply.
VCOgLV 57 0 Reserved. Output for Testing Purpose only at Factory.
AVSS__LV 58 G Ground for LVDS outputs.

AVDDOUTgLVASS 59 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
CH3P_LV_E 60 0 These form the Differential Data Output for Channel - 3 (Even).
CHSNngE 61 o

CLKPALV_E 62 0 These form the Differential Clock Output Even Channel.
cLKN_Lv_E 63 o

CH2P_LV_E 64 0 These form the Differential Data Output for Channel - 2 (Even).
CH2N_ngE 65 o

CH1PALVAE 66 0 These form the Differential Data Output for Channel - 1 (Even).
CH1NLVgE 67 o

CHOPALV_E 68 0 These form the Differential Data Output for Channel - 0 (Even).
CHONALviE 69 o

AVSSAOUTiLV 70 G Ground for LVDS outputs.

AVDDAOUTALV_33 71 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
CH3P_LV#O 72 0 These form the Differential Data Output for Channel - 3 (Odd).
CHSNALV70 73 o

CLKPiLVAO 74 0 These form the Differential Clock Output Odd Channel.
cLKN_Lv_o 75 o

CH2P_LV_O 76 0 These form the Differential Data Output for Channel - 2 (Odd).
CH2N_LV¥0 77 o

CH1PALVAO 78 0 These form the Differential Data Output for Channel - 1 (Odd).
CH1NLVgO 79 o

CHOP_LV_O 80 0 These form the Differential Data Output for Channel - 0 (Odd).
CHONLV70 81 o

Page 151

OPERATION CHECK-4

Condition of Protect Mode

The unit will go into Protect mode under the following conditions.
(T: Thermal sensor temperature)

1 Thermal condition
After 10 minutes of T >= 100 °C
or
Immediately T <= -30 C
or
Immediately T > 150°C
or
Immediately T >= 90" C (if T > 40" C when power is on)
or

Immediately T >= 90 °C (if the unit is powered on longer than 24 hours)

2 DC voltage condition

The sum of dc voltage of 7 channnel speaker outputs is more than 7 V.

3 Current condition
Protect will be on if speaker output ac current >= 35 A.
Protect will not be on if speaker output ac current >= 117 A

This condition is equivalent to OPERATION CHECK-2.
Test wave form:

_T

2 msec 2 msec
20 msec

Condition of Power Supply Control

DSP output=max
(OdBFs)

The power supply voltage(VH or VL) for power amplifiers is changed by the relays: RL6901 and RL6902i

VI-I > VL (At VL, the maxmum speaker outputs are reduced for safety)

T: Thermal sensor temperature

VOLH: Pin #99 input voltage of Main microprocessor: Q2001 (Refer to SD-22A3 and SD-5:G3 of Schematic Diagram.

VL: VOLH >= 045V and T >= 65 aC
or
VOLH >= 2.6V (Longer than 240ms)

VH: Conditions except above

Condition of Cooling Fan Operation
The cooling fan will stop or rotate under the following conditions

STOP:
VOLH < 035V
LOW SPEED:
VOLI-I >= 035V
MID SPEED:
VOLH > =0i55V or T >= 55 °C
HIGH SPEED:

VOLI-I >= 045V and T >= 65 °C

Page 153

TX-SR705/SA705

ADJUSTMENT PROCEDURE-2
IDLING CURRENT ADJUSTMENT

AMPLIFIER PC BOARD
(NAAF-9142)

5
@
HIE;g g
02% i?

1 2A 2an '

1059A

R6044 "
P6084 Trimming

355$ resistor

Trimming
resistor

Trim_ming
reSISIor

-.-@

P5081 R6041 P6082 R6042

P6080 R6040 _ >
T651 Trimming 3351 Trim_m ing Te_st Trim_ming S B R
PW resistor reSISIor pomt resuslor P6086

3+ El |D+ |D+ ID, Tesl
ID» ID- ID' "3- point