Onkyo TXSR 303 Service Manual

Page 1

TX-SR303/303E

Ref. No. 3862

ONKYO SERVICE MANUAL 0.2005

AV RECEIVER

MODEL TX-SR303
MODEL TX-SR303E

RC-SOSS

TX-SR303 Silver model
120V AC, 60Hz

TX-SR303E Silver model

230-240V AC, 50Hz

SAFETY-RELATED COMPONENT
WARNING! !

COMPONENTS IDENTIFIED BY MARK A ()N THE
SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE
CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK.
REPLACE THESE COMPONENTS WITH ()NKYO
PARTS WHOSE PART NUMBERS APPEAR AS SHOWN
IN THIS MANUAL.

MAKE LEAKAGE-CURRENT OR RESISTANCE
MEASUREMENTS TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE
SUPPLY CIRCUIT BEFORE RETURNING THE
APPLIANCE TO THE CUSTOMER.

ONKYO.

IMAGINATIVE SIGHT & SOUND

Page 3

SERVICE PROCEDURE

1.

5.

Replacing the fuses

EE This symbol located near the fuse indicates that the

fuse used is show operating type, For continued protection against
fire hazard, replace with same type fuse, For fuse rating, refer to
the marking adjacent to the symbol.

EE Ce symbole indique que le fusible utilise est e lent.

Pour une protection permanente, n'utiliser que (les fusibles de meme
type. Ce demier est indique 1a qu 1e present symbol est apposre.

REF NO. PART NAME DESCRIPTION PART NO. REMARKS
F901 FUSE 6.3AAUL/T-237 252166 1, <303> <303> : TX-SR303 Only
F901 or FUSE 6.3A-T/UL-ST2 252260 1, <303> <303E> : TX-SR303E(Eur0pean model) Only
F902 FUSE 3.15A-SE-EAK FUSE 252076 1, <303E>
F902 or FUSE 3.15A-SE-TL250V 252242 1, <303E>
F902 or FUSE 3.15A-SE-TL250V 252276 1
F6901 FUSE SA-UL 252198 I
F6901 or FUSE 8AAT/ULAST2 252261 1
F6902 FUSE 8A-UL 252198 I
F6902 or FUSE 8A7T/ULAST2 252261 I
. Safety-check out

(Only U.S.A. model)

After correcting the original service problem perform the following safety check before releasing the set to the customer
Connect the insulating-resistance tester between the plug of power supply cord and terminal GND on the back panel.
Specifications: More than 10Mohm at 500V

. To initialize the unit

1. Press and the hold down the VIDEO 1/VCR button , then press the STANDBY/ON button when the unit is Power on.
2. After " Clear " is displayed, the preset memory and each mode stored in the memory, are initialized and will return to
the factory settings.

. To check version of microprocessor

Main microprocessor Q701 only.

1. Press and the hold down the DISPLAY button , then press the STANDBY/ON button when the unit is Power on.
Version is displayed on FL display only for 3 seconds.

Ex.

Ver.0.50/05131a

2. Press the STANDBY/ON button to Power off.

Memory Backup

The AV receiver uses a battery-less memory backup system in order to retain radio presets and other settings
when it's unplugged or in the case of a power failure.

Although no batteries are required, the AV receiver must be plugged into an AC outlet in order to charge the
backup system. Once it has been charged, the AV receiver will retain the settings for several weeks,
although this depends on the environment and will be shorter in humid climates.

Page 55

TX-SR303/303E

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-9
0201: CS494003CQZ (Multi-Standard Audio Decoder)-8I11

TERMINAL DESCRIPTION

HDATAO, GPIOO

In parallel host mode. these pins provide a bidirectional data bus. These pins can also act as
general purpose input or output pins that can be individually configured and controlled by
DSPC. These pins have an internal pull-up. BIDIRECTIONAL - Default: INPUT

A0. GPIO13 - Host Parallel Address Bit 0, General Purpose IIO

In parallel host mode. this pin serves as the LS Bit of a two bit address input used to select
one of four parallel re isters. This pin can act as a general-purpose input or oulfiut that can be
individually configure and controlled by DSPC. BIDIRECTIONAL - Default: INP T

A1, GP|012 - Host Address Bit 1, General Purpose IIO

In parallel host mode. this pin serves as the MS Bit of a two bit address input used to select
one of four parallel registers. This pin can act as aDgeneraI-purpose input or ou ut that can be
individually configured and controlled by DSPC. BI IRECT/ONAL - Default: INP T

E, RIW, GPI011 - Host Parallel Output Enable, Host Parallel Rm, General Purpose lIO

In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola
parallel host mode, this pin serves as the read-high/write-low control input signal. This pin can
act as a general-purpose input or output that can be individually configured and controlled by
DSPC. This pin has an internal pull-up. BIDIRECTIONAL - Default: INPUT

W, E, GPIOtO - Host Write Strobe, Host Data Strobe, General Purpose IIO

In Intel arallel host mode. this pin serves as the active-low data bus enable input, In Motorola

parallel 0st mode. this pin serves as the read-high/write-low control input signal In serial host

mode. this pin can serve as a general purpose input or output bit. This pin can act as a
eneral-purpose input or output that can be individually configured and controlled by DSPC.
his pin has an internal pull-up.

BIDIRECTIONAL - Default: INPUT

E, GPI09 -- Host Parallel Chip Select, General Purpose |I0

In parallel host mode. this pin serves as the active-low chip-select input signal. This pin can
act as a general-purpose input or output that can be individually configured and controlled by
DSPC. This pin has an internal pull-up. BIDIRECTIONAL - Default: INPUT

HINBSY, GPIOB - Input Host Message Status, General Purpose IIO

This pin indicates that serial or parallel communication data written to the DSP has not been
read yet. This pin can act as a general-purpose input or output that can be individually
configured and controlled by DSPC. This pin has an internal pull-up BIDIRECTIONAL -
Default: OUTPUT

SD_DATA15, EXTA18 - SDRAM Data Bus, SRAM External Address Bus
SD_DATA14, EXTA17
SD_DATA13, EXTA16
SD_DATA12, EXTA15
SD_DATA11, EXTA14
SD_DATA10, EXTA13

Page 63

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-17
0421 : CS42518 (8-Ch Codec with S/PDIF Receiver)-4/4

TERMINAL DESCRIPTION

Pin Name # Pin Description

CX,SDOUT 56 CODEC Serial Data Output (Output) - Output for twos complement serial audio data from the internal
and external ADCs

ADC|N1 58 External ADC Serial Input (Input) - The CS42518 provides for up to two external stereo analog to digital

ADC|N2 57 converter inputs to provide a maximum of six channels on one serial data output line when the (3542518
is placed in One Line mode

OMCK 59 External Reference Clock (Input) - External clock reference that must be within the ranges specified in
the register OMCK Frequency (OMCK Freqx) on page 54.

SALLRCK 60 Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channeL Left or Right, is
currently active on the serial audio data line.

SALSCLK 61 Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface.