Nakamichi OMS 50 Service Manual

Page 2

CONTENTS

NH

10.
11.

General ...................................................................... 2
Pickup Replacement Procedures .................................................... 2
2. 1. Notice in Handling Pickup ............................................... 2
2, 2. Pickup Replacement Procedures ........................................... 2
2. 3. Adjustment After Replacement of Pickup ....................................... 3
Measurement Instruments and Test Discs ............................................... 4
Parts Location for Adjustment ...................................................... 4
4. 1. Parts oanCB Assy ..................................................... 4

4 2. Parts on Pickup ............................ 4
Adjustments .................................... 5
5. 1. Notes ................................... . . . . 5
5. 2. Adjustment Instructions ................................ . . . . 5
Mechanism Assy and Parts List .............................................. . . . . . 1o
6. 1. Synthesis ............................................................ 1o
6, 2. Front Panel Assy (A01) 11
6. 3. Chassis Assy (A02) ..................................................... 12
6. 4. Disc Mechanism Assy (B01) .............................................. 13
6. 5. Rear Panel Assy (302) ................................................. 15
6. 6. Disc Mechanism Sub Ass y (001) ............................................. 15
6. 7. Analog Processor Unit (D01) .............................
Mounting Diagrams and Parts List ..................................
7 1. Photo Transistor P. C B. Ass y .............................. 17
7. 2. Photo Diode P. C. B. Ass y ................................ 17
7. 3. Open End Switch P.C.B. Assy 17
7. 4. Close End Switch P.C.B. Assy 17
7. 5. Eject/Load Switch P.C.B. Assy .............................................. 17
7. 6. Power Switch P.C.B. Assy ................................................. 17
7. 7. Remote Control P.C.B. Assy .............................. 17
7. 8, Pin Jack P.C.B. Ass'y ..................................................... 1s
7. 9. FL Indicator P.C.B. Assy .................................................. 18
7. 10. Auto Power Control P.C.B. Assy ............................................. 19
7. 11. RF PrevAmp. P.C.B. Assy ................................................. 20
7. 12. Power Supply P.C.B. Assy ................................................. 21
7. 13. Control Switch P.C.B. Assy ................... ' ............................. 22
7. 14. Analog Processor P.C.B. Assy . . .............................................. 22
7. 15. D/A Converter 1. C. B. Assy ................................................ 23
7. 16. Main P. C. B Assy ....................................................... 26
Schematic Diagram .............................................................. 27
8. 1. IC Block Diagrams and Descriptions ........................................... 27
8. 2. Waveforms at Major Points ................................................. 37
8. 3. Schematic Diagram ...................................................... 38
Wiring Diagram ................................................................ 39
Block Diagram ................................................................. 40
Specifications ................................................................. 41

Page 34

Description of Dilitnl Filter 10 U507 (SAA'1030)
(See Figs. 8.1.21 and 8.1.22.)

Pin Description of Digital Filter 10:

Signal In] Pin Signal In]

Name fl Desc 'on No. Name Out Description

VBB In --2.5 V 20.5 V mpply. 17 DRCF In Right channel data input. Data should be 16

OS In Offset select input. when connected to hit serial. MSB first. offset binary coded. It
VDDI the data output has a fixed DC should be valid on the falling edge of the
offset of 3%. When connected to VSS the data clock CLCF.
output has no offset. (This pin is connected 18 CLCF In Input data clock. The falling edge of this
to VDDl.) signal defines input data valid.

3 DLFD Out Left channel data output. The data is 14 bit 19 CLOX In Master input clock. Runs continuously at a
serial, MSB first and is valid on the falling nominal frequency of 4.2336 MHZ.
edge of output clock CLFD. 20 DLCF In Left channel data input. See DRCF.

6 CLFD Out Output data clock. nominal frequency 21 STRl In Input 44.1 kHz strobe. The circuits internal
4.2336 ME: (= CLOX). The falling edge of timing chain is synchronized by the rising
this signal defines output data valid. edge of STRI which must run synchro-

7 LAI Out Output 176.4 kHz strobe. The rising edge of nously with CLOX in accordance with the
th's pulse says that the output of a 14I bit timings specified in the electrical
data word has been completed. characteristics.

10 DRFD Out Right channel data output. See DLFD. The rising edge should follow the
11 (TE In Offset binary not input. When connected to completion of the input data stream.
VDD1 the output data is coded as 23 22 RT In Reset test not input. When low resets the
complement. when connected to vss the part of the accumulator not reset in nonnal
output data is coded as offset binary. (This operation to initialize the accumulator for
pin is connected to VSS.) testing. In normal operation should be
12 V53 -- Ground. _ connected to VDDI.
l3 VDD2 In 12V $1096 supply. 23 TE In Test enable not input. when low switches
15 TINR In Test input (R). Right channel test chain the internal circuitry into the sequential
input. In normal operation this pin should scan test mode. In normal operation should
be connected to either VSS or VDDl. be connected to VDDl.
16 TINL In Test input (L). Left channel test chain 24 VDDl In 5V 110% SUBDIV-
input. see TINR.
r- -_-"-I
TIN R at: :g' V33
TIN L |6 |2 V55
Fr 22 TEST --> m 24 vnur
._ ROM
TE 23 its vnoz
I Input I: Rec": . om ur I
DLCF 20 gm. smn Multiplier --> Am -> shif' -> 3 UL
WC" 7) Reqisler Reqisver Mulater Register 01 (DRFD)
CLCF leg: I
5 2' Iiming a Conlro! _
5 CLFD
CLOX x9;-> 37 LAT
L _. _ J
2 l |
os 36

Fig. 8.1.21 Digital Filter 10 SAA'IOSD

35

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\

a iwee-«ewes-ee- ee or a. goose,

{9
Q
£3
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d
E
®
Q
@

(Input)
ELOX
1:ch
m
rum-m
nLcr/aacr an
rum-2mm
sun
(usahzu
(Output)
m H Fl ['1 [-1
rum-r-
mam-Gr
WW lTITmTI'TTTTH m'ITmTHTITI WHTITTTTmTI JTFFTTI'I'I'IITFFI ['[TH'ITH'IT'ITU
mama/m
Fig. 8.1.22 Input/Output Waveform (SAA7030)
Dam IN I I

_ Shin Register
Clock 28

Lalch Enable 2

22 Analog cum
5 GND

25
24
v16 4 23
we 7 2|
Decouphnq
V26) || 20 Binary
Weighled
'9 Cunenl
Vref, 3 ,8 Sources
I4
05:. a ll
Capacitor 5 I2
Vie]. ro

Oscillator a
4- Bit
sum Register

5
Current

Reference |6
Source n

|
l
l
l
L
t
L
L
T
f.
t
t

Fig. 8.1.22 D/A Converter IC TDA1540D

36