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Page 1
ELECTRICAL SPECIFICATIONS
Operati.g Te mper atur e R ange
M ax' P ower Con surt ption 15 degrees C to
40 degrees C
320
millia r tps
Tr
iggeri: 9 Inn t _lIDedance Input Th reshold V oltage Positi
ve edge
l O OK shunted by .Oluf
+1 volt
TTL cortpatible
100 microseconds
1 Hertz to 5
00 Hertz
Mini
.:::!
seWidth
C lod < Rate
outp t D::- ':ve Puse ~;i 'th Clock Rate LSTTL cortpatible
665
microseconds nominal
1 H
ertz to 300 H ertz
Lo
gic Inp ~ Ir:;>eeance I ut es r.old olt age
L ogic
O U
tput Dri ve Active Low
= Disabled
l O OK shunted by .Oluf
1 volt minimum'
T TL compatible
A
ctive Low = Disabled
LSTTL cortpatible
Logic
Ou
tput rivePu se "dd-=." 0 tp ts . .he se_ ected A
cti
ve H igh = Trigger
LST T L cortpatible
2 00 millisecond s n ominal.
S oftware selectable for latched
or
pulsed outputs .
M
EMORY MAP
;, RESS
H EX =:c MAL READ/WRIT E FUNC TION
W
RIT E U17 IlWIl CONTR OLREGIS TER
R EAD Ul7 IIWll STATUS DATAREGISTER
WRI TE U1 7 "WI! TRAN SMIT
DATA R EGISTER
R E AD
U17"
WI !
RECEIVE DATA REGISTER
' f."RITE U1 8 " XII
C R
R EAD U18"X
II
SD R
WRITE U18" X"
TD R
RE AD U1 8 IIX" RDR
W RIT E U 19 "yll CR
READ U 19 "yl1 SDR
w "RIT E U 19 "yll TDR
~ D U19 llyn RDR
i'l' TITE U20 "Zll CR
READ U2 0 IIZI1 SDR
I '.XI E U20 "ZI1 TDR
REA U 20 HZ" RDR
W RITE DR UM TRIGGE R lATCH
W RI E DRUMTR IGG ER lAT CH
' f.~':'E C ONTRO LlA TCH '3L E CONTROL lAT CH
~ D F O OTSWITCH
I NPU
S Ri'7I. D FOOTSWITCH IN PUTS
Page 2
SONG
PRODUCER
TESTIADJUSTMENT ITROUBLESHOOTI NG
I
ncluded on the master diskette is a
complete menu-driven program for testing
the Song Producer hardware module . All
th at is needed to run the test program are
~wo standard "guitar" cables, one MIDI
cable and a footswitch. (Guitar cables may
be used to simulate the footswitch.)
To access the test program, insert the
S
Ong Producer disk and type the following,
W
hen the program finishes loading . the
co mputer will proMPt "READY".
N ext
. type RUN (RETURN) and follow the
enu-driven instructions displayed on the
screen .
IF THE TEST PROGRAM RUNS SUCCESSFULLY. IT
V
ERIFIES PROPER OPERATION OF THE SONG
PRODUCER HARDWARE. Therefore, any problems
encountered
are probably related to user
e
rror and the associated portion of the
o wner's manual should be reread carefully.
If calibration becomes necessary the
program will prompt the necessary
a d
justments. Use a 1/8" (3 mm) flat blade
screwdriver for the only two Song Producer a
djustments - CLOCK PULSE WIDTH and DRUM
P ULSE WI DTH
I
f troubleshooting becomes necessary, the
program will proMPt appropriately .The
co v
er must then be removed using a #1
P hillips screwdriver and a 1/4" phone
plug-to-test probe cable used to complete
the procedure. Tro ubleshooting is best
l eft to qualified service personnel.
Please consult the authorized service
center listo r factory service department
for assistance .
lif-G~= -::-:: 1L it!)
0J ~
!':----C~==n"0I '-" .:..J
.-~-~~
TEST P ROBE CABLE SONG PRODUCER
C I
RCU IT DE SCR IPT ION
THE SONG PR
ODUCER CONSISTS
HARDWARE CIRCUITS :
1. The Dat
a and Address
Bus Buffer
2 . Address Decoder
3 . Control Latch Driver
4. Drum Output Circuit
5.
Clock In and Clock In
Disable Circuit
6. Clock Out and Clock OUt Disable Circuit
7. Fo o
tswitch Inputs NOTE
:ALL
ADDRESSES
ARE
IN HEX AND ARE
FOLLO W
ED
PARENTHETICALLY
BY THEIR
DECIMAL
EQUIVALENT.
8 . MIDI Input and Output
Circuits
9. Interrupt Disable Circuit
The
bus buffers consist of U8 and U9. U8
is a bi-directional bus transceiver
connected to the data bus to buffer
outgoing and incoming data signals to and
from the Commodore 64. The enable and data
direction on U8 is controlled from the
1/01 line and the R/W line from the
Commodore 64. The 1/01 line sets the memory
map boundaries to DEOO ( 56832) to
DEFF (5708 7 ). U9 buffers th e 1/01 line and
R/WQ line, the ~ 2 clock and the first
three address lines from the Commodore 64.
The
address decoder consists of UII and U3
and decodes addresses in the range of DEOO (56832) to DEOF (568 4
7). UII sel ects one
of eight lines by pulling that line low.
Since the least significant address bit is
AI , UII decode
s e verysecond address. For
example,
DEOO w ill stay low for both DEOO
(56832) and DEO I
(5683 3).U3 inhibits any
address
decoding above DEOF (568 4 8).The
decoded
address for each one of the
subsections may be found on the schematic.
The Co n
trol Latch Driv er consists of U7
and U2B a n d is memory mapped at
DEOA
(56842).
A me m oryw rite to thi s address
causes a logic "1" to appear at U7 Pin 3.
T his signal is
"
NANDED" by U2B to provide
a control latch clock which results in
data bus transfer to the appropriate
latches on the falling edge of the ~
2
clock.
DO
=Clock Disab le Output (U4B)
"0" = Dis able
Clock Disable Inp u
t (USB)
" 1" = Disable
Interrupt Disable (USA) "0"
= Disable
Drum Trigger Pulse /
Latch Select
" 0" = Latch . " 1"= Pulse