Kenwood TM 942 A Service Manual

Page 2

TM-742 A/ 742 E/942 A
OVERVIEW "2

List of Destinations ,, :

Model Destination Destination code Model Destination Destination code

TM-742A North America K TM-942A North America K

TM-742A Canada P TM»942A Canada P

TM-742E Europe E TM-942A Other countries M

TM-74ZE Europe E2

TM-742E Europe E3

TM-742A Other countries M

TM-742A Other countries M2

Units for Each Model and Destination

Band Units
n" "am 9" "°- TM'nZAIE TM 942A UT-zas UT-sos UT-zzos UT-1200
K P E 52 E3 M M2 K P M M [50) M (50) K (50) M (10)

Control Unit X53-3460v11 o o 0
Control Unit XSS-SAGO-Zl o 0
Control Unit X53-3460-22 0
Control Unit X53646271 o 0
Control Unit X53-3462-72

Display Unit X54-3130-11 o o o o o o o o o o

ZBTX-HX X57-3790v0l o

50TX-RX X57-3800v01 o

lMTX-RX X57-3580~1 l o o o __
144TX-RX X57-3580~12 O o o o o o o

ZZOTX-RX X57-3810-10 o

MOTX»RX X57-3590-12 o o o

430TX-RX X57-359022 o o

430TX-RX X57~3592-72 O o o o

1200TX»RX X57-3600-1 1 o o o o

7
BAND UNITS

Any of the following optional band units may be installed
in the TM-742A/742EA
The same instructions apply for the Tri-Bander as for the

Dual-bender.
OPTIONAL BAND UNIT
TM-742A
UrS.A. Version UT»285 UT-SOS UT-ZZOS UT1200

TM»742A UT-ZBS UT-SOS UT-1200
TM-742E UT-ZBS UT-SOS UT~12OO

Page 25

TM-742 A/ 742 E/942 A
CIRCUIT DESCRIPTION

18

TM-942A/UT-1200
1200 TX-RX Unit Frequency Configuration

The 1200 MHZ unit incorporates a digital variable
frequency oscillator (VFO) thatfreely can selecta channel
step of 10. 12.5, 20,or 25 kHz with a PLL synthesizer
system.

The frequency in the receive signal channel is mixed
with a frequency of 12003 to 1240.20 MHZ obtained
when a first local oscillation frequency of 600.15 to
620.145 MHz is multiplied by 2 to produce a fist

l240~i299.99MH1

ANT SW

PA TX AMP

intermediate frequency of 59.7 MHz. This frequency is
then mixed with a second local oscillation frequency of
59.245 MHz to produce a second intermediate
frequency of 455 kHz. This is called a double-conversion
system.

The signal in the transmission channel is oscillated
and frequency-divided by a PLL circuit,then multiples
the frequency of 630 to 649.995 MHz by two to
produce a frequency of 1260 to 1299.99 MHz. This
signal is amplified by a straight amplifier. then
transmitted.

/

MCF 455KH1
59.7MH1
/ MlX,lF. DET r-O RA

J.
=1 59.245 MHz

80.3" l240.29MH2

PLL MlC AMP MO

124O-l25939MI-i1

Fig. 18 Frequency Configuration

1200 TX-RX Unit Receive Signal Channel

0 Outline

The received signal from an antenna is passed
through a low-pass filter in the transmission final stage
and sent through a transmission/reception selection
diode switch to the receiving front end. The signal is
then amplified to high frequencies by a microwave
GaAs (gallium arsenidel FET and sent to a dielectric
filter. The unwanted components of the signal are
eliminated by a microwave transistor in another stage
and the dielectric filter. The resultant signal is input to
the first mixer. The front end block is matched by a
microstrip line to ensure high sensitivity and high
reliability. A GaAs FET is used in the first mixer to
obtain a good two-signal characteristic. This signal is
mixed with the first local signal froma PLL circuit
by the first mixer and converted to a first intermediate
frequency of 59.7 MHZ. The unwanted near-by signal
components are eliminated by a two-stage MCF. The

resultant signal is produced as a first intermediate-
frequency signal.

The first intermediate-frequency signal is amplified
and input to FM IF HlC lC2 (KCD04). This signal is then
mixed with a second local oscillation frequency of
59.245 kHz to produce a second intermediate
frequency of 455 kHz. The intermediate-frequency
signal is passed through a ceramic filter to obtain
a sharp characteristic. The signal is then input to an
HlC again. amplified, then demodulated and output
from the HIC.

0 Signal-strength meter
The signal-strength meter output voltage of FM lF
HIC IC2 (KCD04) is supplied to the control unit.

I Shift-register circuit

The F8, CK, and DT serial data from the control unit
are sent to |C5 (BU4094BF) to perform the control
operation outlined in the following table:

Page 29

TM-742 A/ 742 E/942 A

CIRCUIT DESCRIPTION ;

tcr Nimssau In «syncs
1:2 muossas oz IsVIss
r ____________________________________________ '|
' -13 -:i xi 2:: I
: I: it 15* : zv I FM IF uic Kcnu
' I
I
| 5 a 1 Is 5 "2 I4 I! I2 II It: 9 a l ,_
: |-<3J___ -I"\°] °/° I ; 2 g
E? 3 4 I2
i <3- m 5% m} ;
4 II 2 5 4 5 1
I I: a I, _I J J; ,4, I
I CZ I
| o.oI .;n§ g "--j x |
I W cs a,» i
: M N g on 9 0.0m 1'" g o I i
I IsoK " : d g _. I-I-NW-Rs HF}, wfls : 9
| ¢=>n l3 2 ' i, 3 (7K a CM 39K I x;
l 3 ° 3 m, '7» I n
I N E? I 3
| TN I
I.-- Jo---" _-____-'_*'_#E "a ..... "if . £14 I. I
ll I0 9 a 7 e s 4 a z I .l :
o
5 3 Z 5 s I
I- K
g u.
TF3
4:;
Fig. 24 Block diagram of the ALT unit S
§
FTHOZ Input voltage ALT Indicator 2
K
(1-1.48 V Only <1 turns 0N Fix-d volteqe
1.48-2.79 V Both 4 and > turn OFF
2.79-5.0 V Only > turns 0N

Table 20 Relationship between PTHOZ input voltage and
the T indicator
Fig.

DIGITAL CONTROL UNIT
0 OUTLINE

The digital control unit consists of the panel unit which
comprises the keys, rotary encoder circuit and display
circuit, as well as the control unit which comprises the
reset backup circuit, the DTMF circuit, the microphone
key input circuit, the dimmer circuit, etc.

- DATA COMMUNICATION CIRCUIT OF THE PANEL
CONTROL UNIT
Figure 26 shows the data communication circuit of
the panel control unit, So is the serial data output, SI is
the serial data input, and an inverter is located between
them to protect the ports of the microprocessor.
The data communication system is asynchronous,
and a communication rate of 31250bps is realized.
Since the connection is checked once every 0.5 ser
condby the microprocessor of the control unit side, the
power turns OFF when the panel unit is removed.

22

Devi-titan 1 (kHz)

no

IO -5 O 95
25 Relationship between the RM voltage and deviation
during receive
CLOCK IC
INITIALIZATION
- SYSTEM RESET
The POWER ON CLEAR function works automatical-
ly and all logics are initialized in this lC (S-SEZOCF) when
the power is turned ON. The system is reset because the
POWER ON CLEAR bit (D2 of the CNT2 register) is stuck

at "1".

o SYSTEM RESET

All logics are initialized when the SYSCR bit is set to
"1". When cancelling the reset, SCK falls down after
the build-up of CS, as shown in Figure 27.

_| Mm mm 220.: ' Mali mm 5 #5
cs ._.|:1 .-

sfl'-l H H H H n H H MmlmmZZO
Sin - _'l
\___._,._A-__/

on. Iooon
D3

Clmlllelun

Anflrw in I II
Moos regain

sir: I. Svsllm Ilse!

Fig. 27 Reset cancellation timing

Page 44

TM-742 A/ 742 E/942A

CIRCUIT DESCRIPTION

8-bit Shift Register (HD74HC165F): |C7

Terminal Name Function l/O 'Expander
No. terminal name
4 F Parallel inptu terminal (bit 5), FAN delay time setting (bit Oi
lP_FANDL0l "l The time is set in combination with terminal No.5.
E Parallel input terminal (bit 4i Transmission remodeling data (bit 4)
3 0: Remodeling
IP_MDFV7

1: No remodeling

1 FAN Delay Time setting input

FAN control P_FANDL 1 P_FANDL 0
Permanently ON when POWER is ON 0 0
ON during transmission 0 i
.ON during transmission +ON during 1 1 0

minute after and of transmission

ON during transmission +ON during 2
minutes after end of transmission

'TiMlNGCHARTCLOCK I III HI I H II H II HI
SH 1 F'llLOA D

OU'I PUT Q [I L L ll L

H

}

\ |->- SlnCS S/L is stuck at ,H

data are outputted from OH
LOAD at the leading edge of the clock. 37