Kenwood DP 880 SG Service Manual

Page 1

- COMPACT DISC PLAYER

P-SSOSG

SERVICE MANUAL

Remote comroller assy
(IUD-01817053

Metauic cabinet Panel (TRAY) From glass Panel ass'y

[Am-1514702] (A29A0115-03) (8104389904) {A20753477029

Knob (POWER)
(K29-2725-04)

Knob LEVEL)

(ZS-220104)
Phone jack (PHONES)
[E1 1.0162-05}

Fhono jack (LINE OUTPUT)
(E13»0483A05)

Potemiomezer (LEVEL) Power cord bushing
(R29-1001-05J (J42-0083705)

Insulator (FOOT) Phone jack (DIGITAL OUTPUT) "
(J02-0188»15)X4 4513-0131705} 3!
Cap
A .
18097006805) (Eggwe m

" Refer to parts list on page 81.

Page 2

DP-BBOSG

CONTENTS

TRANSPORTATION SCREW .............................. 2
SYSTEM CONNECTIONS ...... .3
CONTROLS AND INDICATORS . ....4
DISASSEMBLY FOR REPAIR .. ....5
BLOCK DIAGRAM ............... ...7

CIRCUIT DESCRIPTION
Description of component.
Semiconductor data.,.

iCie: uPD75208CW-152 tX25-31204 i)

Microprocessor ................................................ 10
|C17: CXAIOSIS iX25-312011)

RF amplitier .................................................. .iS
ICIS: CXAIZMS (X25-3120-t1)

Servo signai processor ........................................ 25
iCiB: CXDIOBSO iXZS-BiZO-Iii

Digitalfiiter ...................................................... 29
IC14: CXD1125O (X25-3120att)

Digitai signai processtng LSI ................................. 31
iC15:CXK58168P~12 (X25-3120-ii)

Static RAM..,, ....................... 53
ICIO, it: PCMSSP-K (XZS-SIZO-iii

D/A converter ................................................... 53

025: STA34IM (X25~3120-11)

Transistor array ............................................... 54

ICIZ: TC17G005AFA0048 (X25-3120-Ii)
D/A distortion compensator .t 54
MECHANISM DESCRIPTION,
1 OPEN/CLOSE operation.
2. Disassembling procedure oi mechanism section ...... 58
ADJUSTMENT ................................................
REGLAGES .
ABGLEICH ..
VOLTAGE TABLES ..
PC BOARD [Component Side Vlew) .
PC BOARD (Foil side View) ...............
SCHEMATIC DIAGRAM ................
EXPLODED VIEW (MECHANISM)
EXPLODED VIEW (UNIT) .
PARTS UST ...........
SPECIFICATIONS

Back cover

TRANSPORTATION SCREW

Before operation, remove the two red screws attached to the
bottom of the unit used during transport from the factory.
Remove both screws using a coin, etc, and, after removing,
retain them together with the Warranty card and other
documents When the unit is so be transported again, be sure
replace the two screws to their originai position:

" For the procedure of attaching the transportation screws,

I Before transport: tighten the transportation
screws
Before transporting this unit, be sure to tighten the two
transportation screws on the bottom of the unit

1. Turn ON the power switch when no disc is loaded .
2' Wait a few seconds until the disc OUT indicator Comes

"ON. The turn OFF the power.

EEK OUT

3. Firmiy tighten the two transportation screws

Page 38

DP-BBOSG

40

CIRCUIT DESCRIPTION

2) Detection. protection and interpolation of frame
synchronizing signals

There are cases during recording where the same pattern
is detected in the data due to the influence of drop-out
and jitter, even if a pattern that is same as the synchroni-
zing signal will not appear.

On the other hand, there also are cases where original
frame synchronizing signal is not detected. Therefore,
protection and interpolation are required besides detection.

The edge portion only of EFM signal (EFMO) latched
With PLCK is converted to "l" and the rest to "0, and
then input is to a 23 bit shift register and a frame synchro-
nizing signal is detected.

In order to protect a frame synchronizing signal, a
window is provided and the same patterns outside of this
window are removed. This width can be selected with
WSE L. If no frame synchronizing signal is located in this
window, interpolation is made with a signal produced by
588-mal counter (4.3218MH2/588 = 7.35l

A 4 bit counter for counting the number of these frames
to be interpolated is provided, and when its count reaches
the level selected with GSE L, GSEM, the window is ignored
and the 4 bit counter is reset with the next frame synchro»
nizing signal. the GTOP terminal is of "H" while this opera-
tion is performed. Further, GFS terminal is of "H" when
the frame synchronizing signal generated by the 588»mal
counter for making interpolation is synchronized with the
frame synchronizing signal from the disc.

The frame synchronizing signal before passage through
the window or the wondow is output out of UGFS (DA05
terminal at the time when PSSL = L.)

WSEL Window Width
0 :3 clock
1 1 7 clock
GSEM Number of frames to = .. ..
GSEL be interpolated UGFS (PSSL L l
o o 2 frames Window
0 i 4 frames window
Frame synchronizrng signal before
i f
0 3 ram passage through window,
1 1 13 frames Window

The timing for write request signal (WREO), Write
Frame Clock (WFCK), etc. is generated based on the pro-
tected and interpolated frame synchronizing signal

3) EFM demodulation

14 bit data is taken out of the 23 bit shift register and is
demodulated to 8 bit data through 14 a 8 conversion
circuit composed of array Iogics. Then a write request
(WREQ) signal is output to the RAM interface block,
and the data is then output to the data bus (DBOB~
DBOI) terminals) of the RAM in accordance with the
OENB signal transmitted from said block.

0 Sub code demodulation
1) Sub code demodulation

synchronizing signals 50, 31 of 14 bit sub codes are
detected out of the 23 bit shift register, and sampling is
made in the timing that is synchronized with WFCK.

After delay of 80 by one frame, $0 + $1 is output out
of SCOR terminal and SO » Si is output out of 8880 ter-
minal (only when SCOR = H.)

Date (P~W) of sub codes only is input to the register
in the timing synchronized with WFCK after EFM demo-
dulation; and sub code 0 is output out of SUBO terminal,
and at the same time, it is loaded in the 8 bit shift register
and is output out of SBSO terminal in correspondence to
a clock from EXCK terminal.

The detials of this timing will be shown in the paragraph
of CPU interface,

2) Sub code 0 error detection

The CRC sub code result is output from the CRCF pin
in synchronism with the SCOR pin. It goes L" when an
error is detected. At the same time as the CRCO flag is
"'1", the CRCF flag is output from the SUBQ pin during
the time from the rising edge of the SCOR pin to the
trailing edge of the SUBO pin. This timing is detialed in
"CPU interface".

Page 48

1 DP-8808G

50

CIRCUIT DESCRIPTION

5) Selection of OFFSET BINARY/2s COMPLEMENT

When the SLOB pin is H", an offset binary signal is
output, and when it is "L", a 25 complement signal is out-
put.
6) Selection of.CD ROM/AUDIO compatibility

When MDl = M02 = MD3 = "H", the player is compa-
tible with a CD ROM and outputs the C2 pointer for each
byte. At the same time, the average value interpolation and
the previous value holding operations are not performed.
For example, when there is an error in the upper 8 bits of
the 16 bits, only the C2 pointer corresponding to the upper
8 bits goes "H, and the lower 8 bits are processed as the
correct data.
0 D/A Interface

The player incorporates a D/A interface output (digital
output) and the digital signal is output from the DOTX pin.
The digital signal is output after passing through interpola-
tion, mute and attenuator circuits. The 4control bits (IDO,
ID1, COPY, EMPHASIS) in the C-bit channel status per-
form a CRC check and are revised only when its OK.

D Timing chart

DA15 1 10 20

0 Countermeasures to defect

To counter a defect, the PDC pin is set to "Hi-Z"
during the time until GFS goes "H" again after inverting
from H" to "L" or after approx. 0.55ms has elapsed,
However, this operation is performed only when the HZPD
flag of register 9 is '1. When HZPD = ,0 it will never be
set to "Hi-Z",

The signal switching between the rough servo in the
CLV-A or CLV-A mode and the PLL servo is output from
the LOCK pin, After the CPS signal is sampled at WFCK/
16, and when the signal is l", the LOCK pin goes H",
when a 0" is present 8 times in a row, the LOCK pin goes
'L

This operation is similar to that for the FSW pin. How-
ever, while the FSW outputs a fixed signal when not in
CLV-A' mode, the LOCK pin always output the above
signal.

30 4D 43

-WWMW
(2-30)

DA11' -i
(C4LFII

LRCK-
(DAIOI

W
WMK'W

f

DAO1~DA16: Rah

L_
:X:

X Lch

DA16' -
(MAL a a. tinsel 1: moisonooaaoaooan-loomomooonoaoaaa

APTR_ / \

APT L

J-_-__L._

'PSSL , "L"

Timing chart of audio output

Page 58

DP-88OSG

60

MECHANISM DESCRIPTION

2-4. Attaching the tray
1) Attach the collars firmly on both sides of the tray to
the four section supporting and guiding the tray as
shown in the Fig. 4.
First attach .the front two section then attach the rear
two sections as shown in Q.

Note: The gear offset of the mechanism after removing]
attaching the tray will be reset automatically by performing
the OPEN/CLOSE operation

2-5. Removing the slider assy

1) Removing the slider tension coil spring attached to the
slider ass'y ( 0 ),

2) Slide the slider ass'y in the direction of arrow Q until
it reaches the position where it can be removed from
the outsert section supporting the slider ass'y.

3) Remove the slider ass'y by pulling out right above in
the direction of arrow ® .

Note : If the slider assy is removed askew, the OPEN/
CLOSE detection leaf switch on the back of the tray
might be bent down.

Fig. 4 Attaching the tray

Slider assylil)

Slider assy tension
coil springiZZl

Fig. 5 Removing the slider assy