Heathkit H 8 Operation Manual

Page 2

Page 2

_HEATHKIT"

TABLE OF CONTENTS

INTRODUCTION .............................. 3

TEST ROUTINES

Initial Test Routine .......................... 4

Memory Test Routine ......................... 9

TROUBLESHOOTING

Precautions for Troubleshooting .............. 15

Troubleshooting Charts ....................... 1 7

OPERATION

Introduction .............................. 25

Modes of Operation ........ r . 26
Decimal Point Operation . . . . i . . i . . 26
Split Octal Display ......................... 27

Use of Front Panel ........................... 28
Register Mode ...................... 28
Memory Mode ............................. 28
Cancel .................................... 30
Loading and Dumping Data ................. 30
Executing a Saved Program . . . ,
Inputting and Outputting ......

THEORY OF OPERATION

System Description .......................... 32
CPU Circuit ........................ 33
F ront Panel (Control Circuit) ......... 36
Power Supply ...................... . . 38
Instruction Set .............................. 3 9

SYSTEM CONSIDERATIONS
Memory Map .............................. 56
1/0 Port Map ................ r 57

Bus Functional Pin Definitions . . . . . i i . 57
System Configurations ................... . 58
APPENDIX
Source Program for the Memory Test Routine . . 61
The Functions of a Computer ................. 63
The 8080 Central Processor Unit . . ......... 68
Specifications ............................... 90
Semiconductor Component Number Index ..... 91
Semiconductor Part Number Index ............ 92
CIRCUIT BOARD XrRAY
VIEWS .............. [Illustration Booklet Page 5)
SCHEMATIC ............................ Fold-in
WARRANTY .................. Inside front cover

CUSTOMER SERVICE .......... Inside rear cover

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Page ?0

CHART 4

(mi 125 pin a) is high.

E (I01 123 pin 3) is low.

w

VES

1/0 360 wrile pulses presem at
ICIDZ pin 13 (Logic probe recom-
mended)

1i IC112 IS NO
2. Wiring error,

iow pulses present at |C1Io pin 24

9

YES

1. IC102 is NIB.
2. Wiring error.

380 address pulses preseni at
IC1IO pin 14

YES

|Ci10 is N/O.

2 msec dockpulse pressmat |C1o2

Tédow pulses presem at bus pin

1 Wiring error
2' anon on nus,

pinii,

YES

IC1UG or Imus is N/o.

IC102 pin 9 is high.

NO

[6102 is N/O.

IES

1, Hold resei and dweck 10112 pin
1
2. |C112 pin 1 is high.

Q

1 Hold reset and check El
|C1MB pin 5).
2. (lCiOdB pin 5) is law.

VES

VES

E§

I. Reset not present at bus pin

2 |C111 or 0119 is N10.
3. Wiring errorr

|C112 is NO,
Proceed to Chart 6.

|C106 is N107
Proceed to Chan 6.

iow in: not preuem tram bus
pin 5 . Check wire harness.

N0

Ir |_C104. IC1E or 10111 is MO,
2, A» "rough A, no! presenl irom
bus pins through
snack wire namess.

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HEATHKITE I

Page 25

OPERATION

This section of the Manual explains features and basic
functions of your H8 Digital Computer. An in-depth
discussion on exactly how to perform the various
front panel functions in writing a program is Con-
tained in the H8 Software Reference Manual.

INTRODUCTION

Refer to Pictorials 6-3 (Illustration Booklet, Page 3]
and 6-4 (Page 29) while you read the following intro
duction.

The Computer front panel contains four status lamps,
nine LED displays, and a iii-key keyboard.

Each of the four status lamps, when lit, indicates the
status of the Computer, as follows:

ION - Indicates the CPU is accepting interrupts.

MON - Indicates you have control from the front
panel.

RUN - Indicates the CPU is in a run condition.

PWR - Indicates that +5 volts is present at the front
panel.

The six left LEDs display the octal ADDRESS. The
three left digits display the high-order address, while
the three center digits display the low-order address,
The three right digits function as the DATA/REGIS-
TER displays. In the Memory Mode, the three right
digits display the data contained at the displayed
address. In the Register Mode, the three right digits
alphanumerically display the register you are addres-
sing and the six left digits display the register con
tents.

The keyboard will be described under Use of the

Frunl Panel.

An important internal feature of the Computer is an
audio alert circuit to signal you when you have made
an error or successfully entered data. This audio alert
circuit has three basic functions:

1. A long beep to verify a Master Reset or an
illegal command.

2. A medium beep to verify successful address
or data byte completion,

3. A short beep to verify key stroke.

This feature is very useful when you are entering a
long program through the front panel. By listening to
the feedback signal, you can determine ifthe Cnmpn-
ter has accepted your data.

Another important feature is the computers ability [0
determine the amount of memory installed upon ini-
tial power-up. It will do this without destroying the
contents of the memory. A detailed discussion of this
feature is contained in the Software Reference Man-

ual.

Because the front panel requires a small amount of
support RAM, you must be careful when entering
data in the first 100 octal locations, starting at the
octal address 040000. You will find these locations
useful when using the front panel as an I/O device. A
discussion on exactly how to access the front panel is
uuiilfliued iii the Suflwnrv Reference Manual.

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rf-IATHKITH

As a result of entering the HOLD state. the CPU ad-
dress bus and data bus will be in their high impe-
dance state. The CPU acknowledges this state with
the HOLD ACKNOWLEDGE [HLDA) pin.

HLDA [output] HOLD ACKNOWLEDGE - The
HLDA signal appears in response to the HOLD signal
and indicates that the data and address bus will go to
their high impedance state. The HLDA signal begins
at:

1. T3 for READ memory or input operation.

2. The clock period following T3 for WRITE mem-
ory or output operation.

In either case, the HLDA signal appears after the ris-
ing edge of $1 and high impedance occurs after the
rising edge of ¢2.

firm-T. [input] INTERRUPT REQUEST _ The
CPU recognizes an interrupt request on these lines at
the end of the current instruction or while halted. If
the CPU is in the HOLD state or if the interrupt enable
flip-flop is reset, it will not honor the request.

RESET (input) ~- While the RES ET signal is activated,
the contents of the program counter are cleared. After
RESET, the program will start at location 0 in mem-

ory The INTF. and HLDA Flip-Finns are also reset. The
flags, accumulator, stack pointer. and registers are not
cleared. NOTE: The RESET signal must be active for a
minimum of three Clock cycles.

MEMR and I/OR [output] MEMORY READ and IN-
PUT/OUTPUT READ - The read control signals are
derived from the logical combination of the appro-
priate Status Bit (orbits) and the DBIN input from the
8080A.

MEMW and How (output) MEMORY WRITE and IN-
PUT/OUTPUT WRITE _ The write control signals
are derived from the logical combing-on of the ap»
propriate Status Hit [or bits) and the WR input from
the 8080A.

RDYIN (input) READY INPUT - Provides an asyn-
chronous wait request to the clock generator which
generates the synchronous READY signal for the mi-

nrnprnnnssnr

Ml [output] The first MACHINE CYCLE - Provides a
signal tn indicate that the CPU is in the fetch cycle for
the first byte of an instruction.

ROM DISABLE (input) ROM DISABLE - An external
provision to disable the on-board ROM.

SYSTEM CONFIGURATIONS

Your H8 Digital Computer consists of the central pro-
cessing unit, front panel, power supply, and mother-
board. The mother circuit board is used for installing
memory and serial and parallel I/O cards. Memory
must be added for the Computer to be operational
Memory size may range from 4K bytes to 32K bytes.
An on-board ROM allows the following commands to
be executed upon power-up.

1. Memory display and alter.
2. Register display and alter.
3. Input and output to and from a port.

4. Load and dump (with and [/0 card and storage
device).

Therefore, the Computer can execute machine lanv
guage programs using the front panel as an I/O de-
vice.

You can add the following Heath accessories to ex-
pand your Computer system:

Heath Memory Card - Contains 4K of static RAM. By
adding the 4K chip set, you can expand [he memory to
8K. A maximum of four Memory Cards (32K total
memory) can be installed.

Heath Parallel I/O Interface - Provides three ports of
parallel l/O. Each port has eight bits input and eight
bits output, with complete hand-shaking available.

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Control Circuitry

The control circuitry is the primary functional unit
within a CPU. Using clock inputs, the control cir-
cuitry maintains the proper sequence of events re-

_ quired for any processing task. After an instruction is
fetched and decoded, the control circuitry issues the
appropriate signals (to units both internal and exter-
nal to the CPU) for initiating the proper processing
action. Often the control circuitry is capable of re-
sponding to external signals, such as an interrupt or
wait request. An interrupt request causes the control
circuitry to temporarily interrupt main program
execution, jump to a special routine to service the
interrupting device, then automatically return to the
main program. A wait request is often issued by a
memory or 1/0 element that operates slower than the
CPU. The control circuitry will idle the CPU until the
memory or 1/0 port is ready with the data.

COMPUTER OPERATIONS

There are certain operations basic to almost any com-
puter. A sound understanding of these basic opera-
tions is a necessary prerequisite to examining the
specific operations of a particular computer.

Timing

The activities of the central processor are cyclical.
The processor fetches an instruction, performs the
operations required, fetches the next instruction, and
so on. This orderly sequence of events requires pre-
cise timing, and the CPU therefore requires a free-
running oscillator clock that furnishes the reference
for all processor actions. The combined fetch and
execution of a single instruction is referred to as an
instruction cycle. The portion of a cycle identified
With a clearly defined activity is called a state. And
the interval hntwenn pulses of the timing oscillator is
referred to as a clock period. As a general rule, one or
more clock periods are necessary for the completion
of a state, and there are several states in a cycle

Instruction Fetch

The first state(s) of any instruction cycle is dedicated
to fetching the next instruction. The CPU issues a read
signal and the contents of the program counter are
sent to memory, which responds by returning the
next instruction word. The first byte of the instruction
is placed in the instruction register. If the instruction
consists of rnan. than one byte, additional states are
required to fetch each byte of the instruction. When

r'fI-IEA HKIT'

the entire instruction is present in the CPU, the pro,
gram counter is incremented [in preparation for the
next instruction fetch) and the instruction is decoded
The operation specified in the instruction will be
executed in the remaining states of the instruction
cycle. The instruction may call for a memory read or
write, an input or output and/ or internal CPU opera-
tion, such as a register-to-register transfer or an add-
registers operation.

Memory Read

An instruction fetch is merely a special memory read
operation that brings the instruction to the CPUe

instruction register. The instruction fetched may then
call for data to be read from memory into the CPU. The
CPU again issues a read signal and sends the proper
memory address; memory responds by returning the
requested word. The data received is placed in the
accumulator or one of the other general-purpose reg-
isters [not the instruction register).

Memory Write

A memory write operation is similar to a read except
for the direction of data flow. The CPU issues a write
signal, sends the proper memory address, then sends
the data word to be written into the addressed mem-
ory location.

Wait (Memory Synchronization)

As previously stated, the activities of the processor
are timed by a master clock oscillator. The clock
period determines the timing of all processing activ-

ity.

The speed of the processing cycle is limited by the
memorys access time. Once the processor has sent a
read address to memory, it cannot prnonnd until the
memory has had time to respond. Most memories are
capable of responding much faster than the proces-
sing cycle requires. A few, however, cannot supply
the addressed byte within the minimum time estab»
lished by the processors clock.

Therefore, a processor contains a synchronization
provision, which permits the memory to request a
wait state. When the memory receives a read or write
enable signal, it places a request signal on the prom-m.
sors READY line, causing the CPU to idle temporar-
ily. After the memory has had time to respond, it frees
the processors READY line, and the instruction cycle
proceeds.

Page 77

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_ _ _ _ I/O nevus: NUMBER
AIS. UNKNOWN INPUT DATA TO
- _. _ _ _ ACCUMULATOR

DH) FLOATING \- J

DBIN
READY
WAIT
W

srATus
INFORMATION
NOTE: ® Refer to Status Word Chart on Page 73.
PICTORIAL 7-6 Input Instruction Cycle
"'2
72
$1
v12
Awu I/o DEVICE
NUMBER
Dm FLB-fim-G - Accumuunon
svnc
DBIN
READY

STAYUS (D (D

INFORMAYIM

NOTE: ® Refer to Status Word Chart on Page 73.
PICTORIAL 7-7 Output Instruction Cycle