Heathkit H 8 5 Manual

Page 1

Heathkit® Manual

for the

SERIAL l/O AND
CASSETTE INTERFACE
CARD
Model H8-5

595-2032-03

, Copyright © 1971
Heath Company

\k H EAT H C O M PA N Y All Highis Reserved
BENTON HARBOR, MiCHIGAN 49° 2 2 Primed in the United Slalssol America

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HEATHK IT' -
KEY HEATH QTY. DESCRIPTION CIRCUIT KEY HEATH QTY. DESCRIPTION CIRCUIT
. No. Part No. Comp. N0. N0. Part No. Comp. No.
CAPACITORS Diodes - Transistors -
Integrated Circuits (oontd.)
31 21-6 1 27 pF ceramic 0113
5 21-153 3 1°00 PF (-001) ceramic C7103- 01041 03 417-821 5 MPSA06 transistor 0101, 0102.
005 0105. 0106,
31 21-27 1 5000 pF (.005) ceramic 0112 0107
5 21476 1 -01 FF cerflrjiic 0114 0:1 417~865 1 MPSA55 transistor 0103
31 21-95 I2 -1 14F 10 0115: 01151 03 4174197 1 FET (selected) 0104
31". 01191 04 442-54 1 araos integrated circuit 10133
0121- 0121 05 443-000 2 4st integrated circuit 10119, i0121
0123- 0 06 442-616 1 LM3302N.LM2901, or i0102
6125- 0127' titans integrated circuit
C1291 029 05 443-10 1 SN7404N integrated circuit 10112
32 25221 3 22 #F WWI" 002 01°91 06 44345 1 SN14oeN integrated circuit IC117
013' 06 443-54 2 SN1403N integrated circuit i0125, 10129
32 25'2 33 "F 3 C 06 «3640 3 SimsaAN integrated circuit 10115, t011s,
33 27-73 1 .047 up Mylar 0101 K2107
33 27" 2 - F W 01°5- 01° 06 443-723 a srmLsoort integrated circuit ICiOfl, 10113.
34 29-5 1 1000 pF (.001) 0107 .0122
WWW? (30° mm") 06 443-730 2 5N74Ls14N integrated circuit 10104, |C105
35 21H 1 23° PF "1' C107 06 443050 1 SN7414N integrated circuit 10127
200 baud) 06 443-020 1 SN74L873N integrated circuit I61 11
07 442-647 1 0040455 integrated c'rcuit |0106
DIODES - TRANSISTORS - IC 3 07 443-53 1 3N7442N integrated circuit i0125
01 5656 7 "149 diode D101 0102 C7 443-90 2 SN74123N integrated i0101, 10103
0103, 0105. cu"
D106 0107 07 443-757 2 sunLStci integrated circuit I0113. 10114
0100' ' 07 443-822 1 SN14L3139 integrated circuit 10126
02 4126,, 1 LED LED101 08 443-754 2 sN14Ls24oN integrated I0101, iCtaz
circuit
NOTE: Transistors (and integrated circuits) are marked for C9 443775 2 325 imegrated WW '0123. 3124
identification in one at the following tour ways:
- a numb CONTROLS - INDUCTOR -swrrcries
2. Type number. (On integrated circuits this refers only
to the "numbers:J and telligzri: bold type. Disregard D1 10-31! 1 5000 n (5 k) mud H1 13
any ° er "um 9'5 ° I D1 10017 1 200 its) control R119
3. Part number and type number. 02 40361 1 100 MH co" L101
4. Part number With a type number other than the one 03 40.1667 2 Inductor (pan of med
shown. relay)
IMPORTANT: If any components are missing irom the D4 60-604 1 Slide SWIM? SW19
sealed to package, return the unopened package tor re- Ds 65-49 2 Reed switch FiLioi, FlL102
placement. Claims tor missing We will not be honored It
the package has been opened.
. . _ _ CONNECTORS
it you toe-ta damaged or defective ICs, order Indivtdual
replacements. Be sure totollow the standard instructions
on the Parts Order Form" and on the inside rear cover of E1 432447 1 girl IemaIe 6°nem' 3'02
th anu I. Saved oct' a 00 enter r
ref": "1:1". I on 3" we °r dam Sad mm" ° 52 432-146 1 15-hole male connector P103
' shell
. g . E3 432-854 16 Round male pin
CAUTION: The integrated circlills packed tn conductive foam E4 4324155 16 Female pin
can bedamaged by static voltage. Since these parts represent E5 432665 1 Shoe connector she"
a considerable portion of the cost 01 the kit, do not remove 7
. them train their packages until you are instructed to do so. 56 32'3 3° SP'W wnnedm
E7 432-903 1 10-pin circuit board P102
connector

DuPont Registered Trademark

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_ -HEATHKITr
KEY HEATH QTY. DESCRIPTION CIRCUIT KEY HEATH QTY; DESCRIPTION CIRCUIT
No. Pan No. 001'an No. No. Part No. Comp. N01 0
Connect; (conga) WIRE - TUBING - CABLE
E8 432932 5 Circuit board pin TPl, TL. 343-11 8' Shielded wire
TPZ, TP3. 344-59 3 Solid while wire
TP-t 344-111 3" Orange stranded wire
E9 432-947 2 25-pin connector S101 344-120 3" Black stranded wire
E10 432-958 1 10-hole connector 8102 344-121 3" While stranded wire
shell 345-67 3' Heal-shrinkable tubing
E11 432-969 1 5-pin circuit board P101 347-1 4' Round 8-wiro cable
oonnedor 347-55 2 Flat 8-wire cable
E12 432-970 1 5pm connector shell 347-60 5' 2-wire cable
E13 266-966 I Connector key
SOCKETS - PLUGS MISCELLANEOUS
F1 434486 2 Phono 54)ka IN. OUT
F2 434498 15 14-pin socket 73-151 1-3l4 Yape
F3 434-299 a 16-pin socket 85-21104 1 Circuit board
Fl 434-811 2 201m socket H1 204-2308 1 Brackel
F5 434-312 2 28-pin socket H2 352-13 1 Silicone grease
F6 438-4 2 Phono plug P104. P105 H3 391-34 1 Blue and while label
F7 435-26 2 Had phone plug P106. P107 H4 404-535 1 4.0 MHz crystal Y101
F8 438-52 2 Subminiamre phone P108, P109 4431253 1 Blank casseIte
plug 490-195 1 Solder braid
HARDWARE Solder
597-260 1 Parts Order Form a
G1 250-56 5 6-32 x 1/4" screw Assembly Manual
62 252-3 3 6432 nut (See Page 1 for
63 254-1 3 #6 lockwasher pan number.)
a 1 V s 1 MCI-1681 2 3 4 5 6 7
Iwrel/era/ljursJ/EmI i l I [ I i I . I I i I I I 1 i, I I i I
l' I I ' I I ' I I I I I I I ' I I I I I I I '
O 5 1 (cm a a A 5 1 n o In H u 1: u «a 10 I7

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-HEATHKIT'

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[

]

6-32 x 1/4"
SCREW

Refer to Detail 4-2A, bend back the two tabs, and
insert the connector on the flat 8-wire cable into
rear panel hole 3. Be sure the connector ribs are
positioned as shown.

Loosen the two screws of cable clamp AG. open
the clamp, route the remaining cables through
the clamp, and then close the clamp on the
cables and retighten the screws.

Install a 6-32 x 1/4" screw through thebottom of
the computer chassis to hold the Card in place.

D0 N01
USE P10

SERIAL [/0
AND CASSETTE
lNTERFACE
CARD

PICI'ORIAL 4-2

BEND BACK

Detail 4-2A

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HEATHKIT '

STATUS READ DEFINITION

In data communication systems, it is often necessary
to examine the status" of the active device to ascer-
tain if errors have occurred or other conditions that
require the processor's attention. The 8251 has
facilities that allow the programmer to read" the
status of the device at any time during the functional
operation. See Pictorial 5-12.

A normal read" command is issued by the CPU with
the CID input at one to accomplish this function.

Some of the bits in the Status Read Format have iden-
tical meanings to external output pins so that the 8251
can be used in a completely Polled environment or in
an interrupt driven environment.

D1

09

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D: 2 I Do

SVNDET

FE

DE

FE TxE RXHDV TxFIDV

SAME DEFINITIONSAS lfO PINS

PARIVV ERROR

m PE flag I; set when . puny
I'm IE «mat It il mm by
«in ER bu at m: Command
lmmninn PE am Ml mmtm
mum at e- 8251.

OVERNUN ERROR

1|. OE mg i! at Man in CPU
does not read a world" Man
the next one hem-m: available

It is me: by the ER bit at the
Oummlnd Innmnimi OE does
not imibimp-mion ot the 8251:
Vacuum the wuiwsly mmun
manna Ix lm.

FRAMING [anon (Async only}
The FE m. in at when a valid
Slap m it no! am n m.

Nd DI MI'V rev, It I: (not
by the ER an or m: Command
Innmmm FE mos not mmbn
m ammo» ol the 3251i

PICIORIAL 5-12

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When current flows through the LED in IC121, the
photo transistor turns on and causes pin 12 of 101220
to go low. IC122D inverts this signal and feeds it to the
data input of the USART. ICIEZD also buffers any
direct 'II'L inputs from pin 3 of P102.

When used as a passive input, R1 5 1 is jumpered out of
the circuit and pins 5 and 6 of P102 are inserted in the
loop with pin 6 to the more positive side. When used
as an active input, R151 is again jumpered, but pin 6 is
jumpered to ground. The loop is connected between
'pins 5 and 10, with the more positive side to pin 5.
R143 provides a current source to the negative supply
line from pin 10. When used as an 118-232 input, pin 6
is jumpered to ground and the signal is applied to pin
5. R151 provides current limiting for the LED input of
IC121.

IC122A afl. and (mi and 0107 provide buffering
for the DTR and RTS command lines from the
USART. These lines aresoftware programmable and
may be used for controlling the serial I/O device.

PORT DECODER

The port decoder causes each IIO port to respond only
to its particular port number. When the CPU addres-
ses an IIO port, the port number is put out on the lower
eight bits of the address bus. These lines are fed to
IC125 and IC126 which may be programmed to re»
spond when certain addresses are present. Due to the
bus structure of the computer. the address [and data]
lines go low when asserted.

The decoder has three sections; IClZBA, IC125, and
ICIZGB. These correspond to the three digits of the
port number. IC126A decodes the most significant
digit. Its selected output goes low and enables IC125
to decode the second digit. Then its selected output
goes low and enables ICIZBB to decode the least sig-
nificant digit. Notice that only even-numbered ad-
dresses are available from [01263. This is because the
USARTs require a pair of ports, one for control words
and the ot_her for data. The least significant bit of the
address (A0) is used to switch the USART between
these ports.

@

The selected output of IC126B goes low when E
enabled. This enables the USART through the Chip
Select pin. The two USART chip select pins may be
interchanged with Port Interchange switch SW101 if
you want the console device to respond to the Load
and Dump address. This is useful when using a tele-
type terminnl's paper tape punch/reader.

The address decoder is active during memory refer-
ences and the USARTS may be enabled. This has no
effect, however, since the 1/0 read and write pulses
would not be present.

CONTROL LOGIC

The signals from the control bus are buffered by
[0127. The fit line goes low during power up
and whenever the system is reset from the computer
front panel. This signal is inverted by IC127E and
resets the USARTS, lC123 and IC124. The least sig~
nificant bit of the address, 30, is inverted and
switches the USARTs between the command (Kc Lo)
and data (-Ao Hi} modes. The 1/0 write line (10W)
causes a word to be written into a USART if it is
enabled. The 110 read line (10R). in conjunction with
the address decoder, causes a word from the selected
USART to be placed on the local data bus.

Either output from the address decoder going low
will cause the output of IC118D to go high. If the 1/0
read line is also high. the output of 1C1 18C will go low
and enable bus driver 1C132, and disable bus receiver
10131. The system clock, ¢2, is inverted by IC127B
and used as the high speed clock for the internal
operation of the USARTs.

DATA BUS BUFFERS

10131 and IC132 form a bidirectional, tri-stete, data
bus buffer. If neither of the ports are being read. IC131
is enabled by the low on (TE, and IC132 is disabled.
This inverts the system data bus and puts it on the
local data bus to the USARTs. Since IC132 is disabled,
its outputs are in a high impedance state and have no
effect.