Accuphase DP 85 Brochure

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Accuphase DP 85 Brochure

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Supports new generation formats with high sampling rates such as 2.8224 MHz/1 bit and 192 kHz/24 bits MDS type D/A converter achieves stunning performance and sound quality D/A converter with printed circuit boards made from Teflon (glass fluorocarbon resin) with low dielectric constant and low loss (✽ Teflon is a registered trademark of DuPont USA.) Ultra jitter-free PLL circuit topology Fully separate processor section with coaxial and optical digital inputs Ultra high-speed digital coupler ensures effective separation between digital and analog sections Digital level control with an adjustment range of 0 dB to –60 dB Balanced and unbalanced analog outputs MDS (Multiple Delta Sigma) is a revolutionary design which employs several delta sigma type converters in a parallel configuration. In the combined output of these multiple converters, conversion errors cancel each other out, resulting in a drastic improvement in all relevant aspects of converter performance: accuracy, S/N ratio, dynamic range, linearity, THD, etc. For the DP-85, this principle has been fur ther refined by enhancing the current-to-voltage converter in the signal adder section for even better stability and top- notch performance. DAC #1 #2 S 1 e1 S2 e2 Sn-1 en-1 Sn en #n-1 #n Digital input S 0 (Signal) e 0(Conversion error) MDS output Signal Conversion error Note the ratio between signal and conversion error. In the MDS output, the error is very small in relation to the signal. For the purpose of synchronizing operation of the D/A converter with the digital audio interface (DAI), a phase-locked loop (PLL) circuit is used which generates a master clock to be used as system reference. As shown in the diagram, the Ultra Jitter-Free PLL Circuit of the DP-85 consists of a preamble detector and a voltage- controlled oscillator (VCO) using a quartz crystal element. The master clock produced by this PLL circuit is totally free from the effects of pulse distortion and jitter. V C O DAI input signal Preamble detector Phase comparator Frequency dividerPreamble signal (pulse distortion removed) Loop filter Master clock output The DP-85 uses six delta sigma converters in parallel, which results in an overall performance improvement by a factor of 2.45 (= √6). [ Digital Processor Section] Features and Functions Ultra Jitter-Free PLL Circuit Further Improved MDS Type D/A Converter Assembly with HS-Link encoder, master clock generator, DAI encoder/ decoder, ultra jitter- free PLL circuit, and other digital signal processing circuits MDS type D/A converter principle Principle of ultra jitter-free PLL circuit MDS D/A converter and analog outputs assembly (with two Teflon PCBs for left & right channels, featuring low dielectric constant and low loss) Supplied remote commander RC-28 Functions include input switching, output level adjustment, direct play, repeat, program, shuffle, etc.